This invention relates to a circuit for applying a voltage to a MOS capacitor memory cell in a semiconductor memory device.
Recent dynamic type memory devices use memory cells, which include MOS capacitors for memory elements having extremely thin insulation films and MOS transistors for transfer gates. These MOS capacitors are constructed of an ultra thin insulation film with one of the electrodes formed on the semiconductor substrate, and the other electrode formed on the insulation layer. The electrode formed on the substrate is connected to a transfer gate MOS transistor and the electrode formed on the insulation film is connected to the power source Vcc, which applies an external voltage. This external voltage is necesary to form a strong inversion state in the substrate surface region of the MOS capacitor.
Memory cells are increasingly being required to store a large number of charges, and with advances in ion implantation technology, there are many cases of changing MOS capacitors from enhancement types to depletion types. In this situation, the surface region of the substrate of the MOS capacitor is normally in the inverted state so that it is necesary to connect one electrode to a voltage source Vcc. Of course, in order to prevent deterioration or damage to the insulation film and to prevent the operation of the memory cell from being affected by momentary fluctuations in the voltage power source Vcc, it is preferable that the voltage of the electrode formed on the substrate be less than Vcc, e.g., the same as ground Vss or 1/2 of Vcc. (This is described in U.S. Pat. No. 4,225,945.)
In the actual mass production of memory devices, in particular, faults in the insulation film will occur, but which still allow the device to operate. In order to ensure the quality of the memory devices it is important to screen for faulty goods before shipment. This screening presently consists of a variety of different stress application tests such as a bias-temperature (B-T) test and a regular test (normal operation test) in the case of LSI (large scale integration) memory. These tests are stress accelerated tests in which a voltage (e.g. 7-8 V), which is higher than the normal operation voltage (e.g. 5 V) is applied. In these kinds of tests, when there is a fault in the insulation film, the fault will forcibly be destroyed so that faulty goods can be screened.
This screening, which applies a high external voltage, cannot be applied to LSI memory devices in which the MOS capacitor of the memory cell has a low voltage of ground, Vss, or 1/2 of Vcc applied. There remains, then, the problem of maintaining product quality in LSI memory devices. Also, with LSI memory in which a voltage of 1/2 Vcc is applied to the MOS capacitor, the burn-in time must be increased to raise the reliability of the screening, which results in an increase in overall production time and test costs, as well as requiring various test equipment such as a thermostatic chamber for the burn-in test.